1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of dummy gates and its manufacturing method.
2. Description of the Related Art
Generally, a semiconductor device such as a metal oxide semiconductor (MOS) device is constructed by a gate and source/drain regions manufactured in self-alignment with the gate.
In a first prior art method for manufacturing a semiconductor device, a gate conductive layer is deposited on a monocrystalline silicon substrate. Then, a photoresist layer is coated on the gate conductive layer. Then, the photoresist layer is exposed to ultraviolet light via a photomask. In this case, for example, the photomask has a tight pattern such as a comb-shaped gate pattern and a coarse pattern such as an isolated gate pattern. Then, the photoresist layer is developed, so that the photoresist layer is patterned.
Next, the gate conductive layer is patterned by an etching process using the photoresist layer as a mask, so that the gate conductive layer is patterned.
Finally, the photoresist layer is removed. Thus, the gate conductive layer has gate patterns corresponding to the gate patterns, respectively. This will be explained later in detail.
In the first prior art method, even when the photomask has the same gate length, the gate length of the comb-shaped gate pattern of the gate conductive layer is smaller than the gate length of the isolated gate pattern of the gate conductive layer. This is due to the proximity effect caused by light diffraction and the amount of the gate conductive layer redeposited on the sidewall thereof after the etching process of the gate conductive layer.
In a second prior art method for manufacturing a semiconductor device (see JP-A-10-200109), a dummy gate is interposed between the gates, so as to homogenize the proximity effect and the amount of the redeposited gate conductive layer. This also will be explained later in detail.
In the second prior art method, however, when designing a photomask for the dummy gate, additional design time for dummy patterns thereof is required. In particular, if a plurality of kinds of comb-shaped gate patterns are present, the additional design time is enormously large, which would increase the turnaround time, thus increasing the manufacturing cost.